An efficient and flexible hardware support for accelerating synchronization operations on the STHORM Many-core architecture

Conference of 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 ; Conference Date: 18 March 2013 Through 22 March 2013; Conference Code:100164International audienceThe current trend in embedded computing consists in increasing the number of processing resources on a chip. Following this paradigm, the STMicroelectronics/CEA Platform 2012 (P2012) project designed an area- and power-efficient many-core accelerator as an answer to the needs of computing power of next-generation data-intensive embedded applications. Synchronization handling on this architecture was critical since speed-ups of parallel implementations of embedded applications strongly depend on the ability to exploit the largest possible number of cores while limiting task management overhead. This paper presents the Hard Ware Synchronizer (HWS), a flexible hardware accelerator for synchronization operations in the P2012 architecture. Experiments on a multi-core test chip showed that the HWS has less than 1% area overhead while reducing synchronization latencies (up to 2.8 times) and contentions