A fast and accurate methodology for power estimation and reduction of programmable architectures

Conference of 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 ; Conference Date: 18 March 2013 Through 22 March 2013; Conference Code:100164International audienceWe present a power optimization methodology that provides a fast and accurate power model for programmable architectures. The approach is based on a new tool that estimates power consumption from a register transfer level (RTL) module description, activity files and technology library. It efficiently provides an instruction-level accurate power model and allows design space exploration for the register file. We demonstrate a 19% improvement for a standard RISC processor