Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs

In this paper, a variety of flip-flop (FF) designs fabricated in a commercial 28-nm Fully-Depleted Silicon on Insulator (FDSOI) technology are evaluated for their single-event upset performance with ions and pulsed laser experiments. These FF designs consist of unhardened DFF, hardened DFF with stacked transistors in the inverters, and the layout-optimized DFFs. These DFFs were exposed to alpha particles and heavy ions (HIs). None of the hardened DFFs exhibit any errors up to a Linear Energy Transfer (LET) of 50 MeV* cm(2)/mg under normal irradiation, and a layout-based hardened DFF started to see errors at a LET of 50 MeV* cm(2)/mg with the tilt angle of 600. The testing data substantiates effective SEU reduction of these hardened designs. Two-photon absorption (TPA) laser experiments were carried to test these DFF designs, and the results showed that pulsed laser may not be a valid tool to evaluate the FFs designed with nano-scale SOI stacked structures. This brings new challenges in laser hardness assurance for RHBD designs.This work was supported by the Natural Science and Engineering Research Council of Canada, and CMC Microsystems