A Low-Power Incremental Delta-Sigma ADC for CMOS Image Sensors

This brief presents a second-order incremental delta-sigma analog-to-digital converter (ADC) for CMOS image sensors (CISs). The ADC that employs a cascade of integrators with a feedforward architecture uses only one operational transconductance amplifier (OTA) by sharing the OTA between the first and second stages of the modulator. Further power and area savings are achieved by using a self-biasing amplifier and the proposed level-shifting technology, which allows active signal summation at the quantizer input node without using an additional OTA. Fabricated in the 0.18-mu m CIS process, the 10-bit ADC occupies a die area of 0.002 mm(2) and consumes 29.5 mu W from a 1.8-V supply. The measured differential nonlinearity and integral nonlinearity are less than +0.22/-0.2 and +0.71/-0.89 LSB, respectively. Operating at 20 MS/s, the ADC provides signal-to-noise-distortion ratios of 57.7 and 62.3 dB for signal bandwidths of 156.25 and 78.125 kHz, respectively.This work was supported in part by the IC Design Education Center [Electronic Design Automation Tool, Multiproject Wafer (MPW)] and in part by the Space Core Technology Development Program funded by the Ministry of Science, ICT, and Future Planning under Grant NRF-2012M1A3A3A02032428. This brief was recommended by Associate Editor L. H. Corporales