Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 x nm technology

This paper investigates the failure mechanism manifested in DDR3 SDRAMs under 3 x nm technology. DRAM cells should retain the stored value if they are refreshed within the cell retention time of 64 ms at minimum. However the charge in a DRAM cell leaked faster, and the values of the stressed cells could not be retained with valid yet stressful hammered accesses to a row. An experiment of accelerated discharging by hammered accesses was duplicated by a SPICE simulation with a TCAD device model of a DRAM cell. Experiments with commercial DDR3 discrete components from three major memory manufacturers were performed to confirm the validity of the SPICE simulation. The contributions of each in triggering and accelerating the failure mechanisms are investigated depending on the three test parameters tu, data pattern, and temperature based on the experimental results. In the experiments, all commercial DDR3 components failed much earlier than the specified limit of allowed accesses. In the worst condition, the failure in a normal cell of a component occurred at 200 K, which is 15.23% of the permitted cell retention time. (C) 2015 Elsevier Ltd. All rights reserved.Authors greatly appreciate the help given by Dr. ShiJie Wen and Richard Wong at Cisco Systems, Inc. for the field application discussions of this paper./This research was supported by the Cisco Systems, Inc. and MOTIE (Ministry of Trade, Industry & Energy (project number #) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.We want to add the acknowledgement as described in the article.Due to the editing limitation, we marked the boundary of the paragraph as "/"