On-chip interconnects for next generation system-on-chips

Brinkmann A, Niemann J-C, Hehemann I, Langen D, Porrmann M, Rückert U. On-chip interconnects for next generation system-on-chips. In: ASIC/SOC Conference, 2002. 15th Annual IEEE International. IEEE; 2002: 211-215.Today's deep submicron fabrication technologies enable design enginefrs to put an impressive number of eomponfnts like micropmeessors, memories, and interfaces on a single microchip. With the emergence of 100 nm processes, billions oftransistors can be integrated on one die and form a parallel system, consisting out of thousands of components. To handle this impressive number of components it is important to provide a communication infrastructure which is able to scale with the capabilities of upcoming fabrication technologies and which provides the foundation for efficient on-chip communication protocols. This paper addresses the architectural requirements which are coupled with the transfer of well known techniques from parallel computers unto the design of Secs and proposes an on-chip architecture which is based on active switch bores. We will show that this architecture is able lo fill the existing design gap between an efficient use of the design space and the design complexity with reasonable resource requirements