Hardware Accelerated Data Analysis

Franzmeier M, Pohl C, Porrmann M, Rückert U. Hardware Accelerated Data Analysis. In: IEEE Computer Society. Technical Committee on Parallel Processing, Technische Universität Dresden. Technical Committee on Parallel Processing, eds. Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on. Los Alamitos, Calif. : IEEE Comput. Soc; 2004: 309-314.In this paper we present a massively parallel hardware accelerator for neural network based data mining applications. We use Self-Organizing Maps (SOM) for the analysis of very large datasets. One example is the analysis of semiconductor fabrication process data, which demands very high performance in order to achieve acceptable simulation times. Our system consists of Processing Elements (PEs) working completely in parallel on the task of SOM simulation. We will show the scalability of the system concerning precision and number of PEs, as well as the flexibility of the system regarding size and shape of the simulated maps. The possibility of emulating virtual maps (one PE emulates more than one neuron) enables the computation of maps with more neurons than PEs. Benchmarking results of our FPGA (Field Programmable Gate Array) based implementation of the system show the high performance of our accelerator