Voltage Island Partitioning Based Floorplanning Algorithm

As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.This work was sponsored by ETRI SW-SoC R&BDCenter, Human Resource Development Project. Thisresearch was also supported by the MKE (The Ministryof Knowledge Economy), Korea, under theITRC(Information Technology Research Center) supportprogram supervised by the NIPA(National IT IndustryPromotion Agency) (NIPA-2012-H0301-12-1011). TheIDEC provide research facilities for this study