Automated Tool To Generate Global Clock Distribution For Spine Structure

Clock is a signal which synchronizes the logic as well as register read/write activities of a synchronous circuitry. Therefore a good way to design a reliable clock distributor network is always the top priority in IC design. Clock spine is well known for the robustness in clock signal quality delivered. Spine structure had shown good performance in terms of skew, jitter and OCV. Thus this scheme is popular for the high speed circuitry such as CPU chipset design. However, the clock spine is not commonly employed in SoC, due to the design as well as the validation complexity of this scheme. Many SoC design toolsets do not support this scheme up until now. So in this thesis, an automated methodology will be introduced and proven to integrate clock spine into a SoC to distribute a high frequency clock signal. These include the know-how and automation of the methodologies to minimize the complexity of designing the clock spine