Criticality Stacks Implemented via Kernel Frequency Governor for Power Savings in ARM Mobile Architecture

With the advent of mobile computing devices such as smartphones, modern mobile processors are designed by compromising two opposite characteristics. In one hand, performance needs to be maximized in order to hold up with increasingly demanding applications such as virtual reality, real-time image processing, and intense multitasking. On the other hand, power consumption needs to be minimized, these devices typically run off portable batteries which have had unchanged capacities throughout the last half of the decade. The two methods to have performance on demand, and regulate power consumption are having two different types of processors a.k.a big.LITTLE (one perfomance oriented and one energy saving oriented) and Dynamic Voltage-Frequency Scaling (DVFS). Ideally, performance scales linearly with the frequency of the processor; however, most of the systems on a SoC run slower than the CPU making an increase in CPU frequency not result in an increased performance because the processor is idle or waiting. On the contrary, power consumption increases as a function of the cube of the frequency. Determining how to adapt frequency in order to maximize performance while optimizing energy consumption is the objective of DVFS. The gap between big and LITTLE processors is shrinking in modern mobile architectures, this necessitates more aggressive DVFS algorithms research. This study aims at adapting a DVFS algorithm that uses Criticality Stacks applied to scalable for the ARM microarchitechture using the Linux kernel. This algorithm has been tested in simulated hardware with generic benchmarks through pseudo-hardware implementation. A parallel research in Texas A\&M is working into adapting this algorithm into a software implementation via the Linux kernel in a x86 architecture. Forking from that code, the algorithm was adapted to work on ARM on two separate Single Board Computers. As a result the algorithm was tested in multiple versions of ARM with a different range of frequencies and varying architecture complexities. Finally the Algorithm was adapted to be used to determine CPU migration mechanisms that are implemented in ARM big.LITTLE The end result of this research is the verification of the previous simulated hardware which yielded 12\% powersavings with 4\% reduction in performance. Testing the algorithm in real silicon allowed to validate these results and as well as the feasibility and constraints of this implementation