Virtual-Channel Based Wormhole NoC on FPGA for ForSyDe/NoC System Generator Tool Suite

Nowadays, the number of processors integrated on system-on-chip (SoC) increases rapidly and makes multiprocessor system-on-chip design (MPSoC) a regular feature of the embedded system. [25] To support the communication between several homogeneous or heterogeneous processors a communication infrastructure, Networkon-Chip (NoC) technology was raised more than ten years ago. Decades of research provides the NoC area with an increasingly sophisticated knowledge system. A wide variety of NoC systems are developed and evaluated. To simplify the design flow of NoC systems, a NoC System Generator Tool (NGS) [23] [25] [26] is developed by researchers of Royal Institute of Technology. It aims to generate NoC systems with different topology, size, processing elements, and network protocols on FPGAs. NoC routers are central parts in modelling NoC communications. In the current version, Nostrum router is used as only supported communication backbone. This project starts from an analysis to NoC theory and steps into important aspects related to NoC router design to implement a register transfer level (RTL) synthesizable wormhole (WH) router in VHDL for NGS tool. WH router is a comparatively old however widely used NoC router structure. A Virtual-Channel (VC) based flow control is adopted in this design to improve the performance. After implementing the WH router, functional tests on a single router, 2×2 and 3×3 WH Router based network are performed on Modelsim 10.0. VHDL test benches with “textio” operations are prepared to generate a clear report to reveal packets’ transfer details in the network. The router and 2×2 network is synthesized on Quartus II for the Cyclone IV E FPGA family to compare the area overhead with Nostrum NoC