A mapping strategy for resource-efficient network processing on multiprocessor SoCs

Grunewald M, Niemann J-C, Porrmann M, Rückert U. A mapping strategy for resource-efficient network processing on multiprocessor SoCs. In: European Design Automation Association, ed. Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings. Vol 2. Los Alamitos, Calif. : IEEE Comput. Soc; 2004: 758-763.Hardware architectures based on a field of hardwareextended processors can provide flexible computing power for applications where parallelism can be exploited. For multiprocessors, the assignment of functionality to execution units can have a great impact on the performance. Additionally, finding the optimal mapping can be a timeconsuming task. We present a multiprocessor architecture along with a suitable design method that includes an automated solution to the mapping problem. Our hardware architecture employs a network-on-chip (NoC) to achieve a high degree of scalability for the application and for the system in respect to future integration technologies.We also show how to reduce the packet buffer requirements with a proper scheduling strategy and present first estimates for the resource consumption of an application targeted for mobile networking