Parametric Reliability of Low Power Adiabatic SRAM

This paper presents our attempt to recover back energy that is stored in the bit lines and in the cell and reused it by a phenomenal technique of energy recovery known as adiabatic principles. By the application of this adiabatic driver the loss of energy to the ground during ‘1\u27to‘0\u27 transition in SRAM is reduced to a greater degree. In this paper the performance of the conventional 6T SRAM circuit is compared with the performance of the Adiabatic 6T SRAM. In the adiabatic SRAM good high degree of power reduction is reported. By applying the aforementioned technique same SRAM is investigated by varying technology. Another parameter such as delay and power delay product (PDP) is also been calculated for all the SRAM. All the circuits are simulated in HSPICE and delay is calculated using Cosmo scope