High Performance Sense Amplifier based Flip Flop Design using GDI Technique

In this paper, a new approach is taken to design sense amplifier based flip-flop (SAFF) to improve performance of this device which is most frequency used in memory devices. With this, problem of cross coupled SR latch in existing SAFF (NAND latch) is removed. The new flip-flop uses a new output stage latch topology using GDI technique that significantly reduces power consumption and has improved power-delay product (PDP). Various topologies along with their layout simulations have been compared with respect to the number of devices, power consumption, power-delay product, temperature sustainability in order to prove the superiority of proposed design over existing conventional CMOS-NAND design. The simulation has been carried out on Tanner EDA tool on BSIM3v3 45nm technology