Implementation of High Speed MAC VLSI Architectures, Based on High Radix Modified Booth Algorithm

Now a day the multimedia communication and digital signal processing systems are increasing which demand for high speed, low power consumption and lower delay. Addition as well as Multiplication is one of the key features of such systems. It is thought to propose a new architecture of multiplication and accumulation unit for parallel processing for addition and multiplication. The proposed architecture uses modified booth algorithm, Wallace tree and carry save adder. Modified Booth algorithm is suggested to reduce the partial products and CSA is utilized for improving the design speed. The proposed design is developed, simulated and synthesized using Xilinx ISE showing the results in terms of reduced delay and lower power