Architecture, design and technology guidelines for crosspoint memories

International audienceWhile standalone Flash memories (NAND) are facing their physical limitations, the emergence of resistive switching memories (RRAM) is seen as a solution for high density, low cost and low energy NAND replacement candidate. However, it has been shown that deeply scaled, high density RRAM architectures, such as crosspoint, suffer of voltage drop effects (IR drop) in metal lines, periphery overhead and metal line charging time due to injected current during programming operations and sneaking currents through unselected bitcells. In this work, we first propose several innovative models for IRdrop, periphery overhead and array-line charging time accounting for in-array multiple bit-write operation. Then, we introduce a new methodology for crosspoint memory design to determine IRdrop, periphery overhead and timing associated with the optimal characteristics of 1 selector-1 resistance (1S1R) device. We apply the proposed methodology to various half metal pitch memory technology nodes (from 50nm to 15nm) and to several written word sizes (from 1 to 32 bits). We show that for 1 bit programmed per array, the RRAM programming current has to be lower than 30µA and the selector leakage current lower than 10nA and that limitations increase as soon as multiple bits are written simultaneously in the same array. This, suggests massively parallel multi-bank write of a small number of bits per array, as the best solution for the RRAM memories to be competitive with NAND memories Keywords—RRAM, crosspoint memory, crossbar memory, 1S1R NVM device, NV