cited By 1; Conference of 8th International Workshop on Network on Chip Architectures, NoCArc 2015 ; Conference Date: 5 December 2015 Through 5 December 2015; Conference Code:119170International audienceIn this paper we introduce a novel MILP formulation for the problem of mapping tasks and routing communications on multi-core systems with power minimization objective. The cores have several power consumption modes. Dynamic and static power consumptions are modeled independently and the dynamic power consumption depends on core load rate. Three types of communication routing are examined: single-path, multi-path and fractional multi-path. Initially a mathematical model is introduced and afterwards a lin- earized mixed-integer program formul...
The orchestration of communication of distributed memory parallel applications on a parallel compute...
ISBN 978-1-4577-1053-7International audienceThe advent of the Deep Submicron technology opens the wa...
To fulfill the need of intensive embedded computations, architects have proposed Network-on-Chip (No...
cited By 1; Conference of 8th International Workshop on Network on Chip Architectures, NoCArc 2015 ;...
International audienceWe investigate the routing of communications in chip multiprocessors (CMPs). T...
We investigate the routing of communications in chip multiprocessors (CMPs). The goal is to find a v...
Abstract—With an increasing number of processing elements being integrated on a single die, networks...
Modern computing chips are composed of multiple, simple, low-power processing cores. Increasing the ...
International audienceThe search for optimal mapping of application (tasks) onto processor architect...
Many-core architectures are becoming a standard design alternative for embedded systems. The force t...
International audienceMulti-core Real-time Systems (MRS) powered by a battery have been adopted for ...
Energy and power density have forced the industry to introduce many-cores where a large number of pr...
The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce...
With an increasing number of processing elements being integrated on a single die, networks-on-chip ...
This work addresses a research subject with a rich literature: task mapping in NoC-based systems. Ta...
The orchestration of communication of distributed memory parallel applications on a parallel compute...
ISBN 978-1-4577-1053-7International audienceThe advent of the Deep Submicron technology opens the wa...
To fulfill the need of intensive embedded computations, architects have proposed Network-on-Chip (No...
cited By 1; Conference of 8th International Workshop on Network on Chip Architectures, NoCArc 2015 ;...
International audienceWe investigate the routing of communications in chip multiprocessors (CMPs). T...
We investigate the routing of communications in chip multiprocessors (CMPs). The goal is to find a v...
Abstract—With an increasing number of processing elements being integrated on a single die, networks...
Modern computing chips are composed of multiple, simple, low-power processing cores. Increasing the ...
International audienceThe search for optimal mapping of application (tasks) onto processor architect...
Many-core architectures are becoming a standard design alternative for embedded systems. The force t...
International audienceMulti-core Real-time Systems (MRS) powered by a battery have been adopted for ...
Energy and power density have forced the industry to introduce many-cores where a large number of pr...
The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce...
With an increasing number of processing elements being integrated on a single die, networks-on-chip ...
This work addresses a research subject with a rich literature: task mapping in NoC-based systems. Ta...
The orchestration of communication of distributed memory parallel applications on a parallel compute...
ISBN 978-1-4577-1053-7International audienceThe advent of the Deep Submicron technology opens the wa...
To fulfill the need of intensive embedded computations, architects have proposed Network-on-Chip (No...