Impact of Device Layout and Annealing Process During the Passivation of Interface States in Presence of Silicon Nitride Layers

This paper reports the experimental evidence of anomalous electrical characteristics of large test structures for the characterization of both silicon-oxide-nitride-oxide-silicon (SONOS) and MOS gate stacks featuring nitride caps. The anomaly has been studied on devices featuring different layouts and it has been attributed to the property of silicon nitride layers to block the diffusion of hydrogen used for the passivation of the Si/SiO2 interface dangling bonds. Since the hydrogen passivation can occur only from the lateral sides of the device, our findings imply restrictions on the dimensions and on the layout of the test structures used to study the electrical properties of the gate stacks in SONOS or in large MOS devices featuring protective nitride caps