A 2.5 Gb/s high-speed serial transmitter for automotive applications has been designed and a circuit/package/board integrated simulation procedure has been set up, enabling the co-design of High-Speed-Serial Interfaces. This simulation methodology employs transistor level models of the transmitter combined with physical-based models of the transmission channel, thus no simplified behavioral models are needed. Model/hardware correlation is reported, including eye closure and jitter effects. Good mutual agreement is found between experiments and simulations
This paper presents innovative compressed macro-models of high-speed digital transceivers for system...
This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling an...
In today’s demand for faster data rates and more features to be integrated on single printed circuit...
A 2.5 Gb/s high-speed serial transmitter for automotive applications has been designed and a circuit...
A 2.5 Gb/s high-speed serial transmitter for automotive applications has been designed and a circuit...
The goal of this PhD has been to model, design and characterize a 10Gbps serial interface suitable f...
Circuit/system level simulations are employed to assess the performance of a 10 Gbps transmitter for...
In this paper, the design and applications of highspeed interconnect transceivers are presented. Ser...
2 This paper details new simulation techniques for serial link Signal Integrity analysis at data rat...
This work reports about the system level design of a transmitter for the next generation of High-Spe...
High-speed wireline transceivers are analog/mixed-signal electronic circuits in charge of transferri...
We present and validate against experiments a modeling approach for high-speed serial links that com...
We present and validate against experiments a modeling approach for high-speed serial links that com...
We present and validate against experiments a modeling approach for high-speed serial links that com...
University of Minnesot Ph.D. dissertation. November 2008. Major: Electrical Engineering. Advisor: Dr...
This paper presents innovative compressed macro-models of high-speed digital transceivers for system...
This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling an...
In today’s demand for faster data rates and more features to be integrated on single printed circuit...
A 2.5 Gb/s high-speed serial transmitter for automotive applications has been designed and a circuit...
A 2.5 Gb/s high-speed serial transmitter for automotive applications has been designed and a circuit...
The goal of this PhD has been to model, design and characterize a 10Gbps serial interface suitable f...
Circuit/system level simulations are employed to assess the performance of a 10 Gbps transmitter for...
In this paper, the design and applications of highspeed interconnect transceivers are presented. Ser...
2 This paper details new simulation techniques for serial link Signal Integrity analysis at data rat...
This work reports about the system level design of a transmitter for the next generation of High-Spe...
High-speed wireline transceivers are analog/mixed-signal electronic circuits in charge of transferri...
We present and validate against experiments a modeling approach for high-speed serial links that com...
We present and validate against experiments a modeling approach for high-speed serial links that com...
We present and validate against experiments a modeling approach for high-speed serial links that com...
University of Minnesot Ph.D. dissertation. November 2008. Major: Electrical Engineering. Advisor: Dr...
This paper presents innovative compressed macro-models of high-speed digital transceivers for system...
This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling an...
In today’s demand for faster data rates and more features to be integrated on single printed circuit...