Power Optimization of Image Filtering with FPGA

High speed real time video processing puts a lot of demand on hardware and Field Programmable Gate Arrays (FPGA) are becoming more popular for this. What makes them interesting in this field is their inherent concurrency which make them ideal for high speed applications. Higher demands for energy efficient solutions require the designer to have knowledge on how different implementations on the FPGA effects the power consumption. Therefore, a study on power consumption for image filtering with FPGA was conducted. Two image filtering algorithms are implemented on a FPGA with the goal of reducing the power consumption for real time image filtering by optimising the implementations on the FPGA. To reduce the power consumption three main areas where examined: optimizing the algorithm, using the different hardware capabilities that come with FPGAs and working with different clock speeds. The different approaches were simulated in a power estimator to evaluate the effects on the power consumption before implementing them on a FPGA and measuring the results. In this project it was determined that lowering the frequency and utilizing the resources to the full extent can have a positive impact on the power consumption. The results were too small for the accuracy of the amperemeter used to be able to make any conclusions. Larger systems with multiple FPGAs might show more noticeable power savings. More knowledge in Hardware Description Language (HDL) programming and resource managing could lead to even lower power consumption