Ultra-Low Power Analog-To-Digital Converter For Medical Application With Emphasis On Dynamic Comparator

This thesis project proposed an ultra low power analog to digital converter for medical application that emphasis on dynamic comparator. The overall schematic design consumed 7 nW of power at 10 kS/s sampling frequency. This thesis highlighted on designing two main components which are the Digital-to-Analog Converter (DAC) and the dynamic comparator. The circuit was realized by using Mentor Graphic tools with technology file (0.18µm CMOS Technology) provided by Silterra. The objective of this thesis project is to achieve low power consumption and small area Successive Approximation Register (SAR) ADC design that is suitable for medical application. SAR ADC is composed of three main components which are DAC, comparator and logic register. In SAR ADC, DAC and comparator consume most of the area and power consumption respectively. Segmentation technique was employed in DAC which brings two DAC architecture into one design