Investigation On Inter-Layer Dielectric Processed By Chemical Mechanical Polishing And Spin-On Dielectric For Complementary Metal-Oxide-Semiconductor Compatible Devices

Surface planarization of the thin film layers that constitute the interconnects in the backend process of integrated circuit (IC) has become a critical need with the increasing number of metal levels. Planarization, globally and locally, needs to be achieved using the most efficient planarization methods available in the complementary metal oxide semiconductor (CMOS) IC fabrication industry. Spin-on dielectric (SOD) coating is a planarization method has long been used by the semiconductor industry. Since it uses liquid silica precursor, it creates particle defects either during storage or coating process because the evaporation of the liquid solvent leaves solid particles. The planarization degree is acceptable at sub-micron gap width but becomes worse at wider gap width. Chemical mechanical polishing (CMP) is another planarization method that is used by semiconductor industry for dielectric polishing. It is found that CMP is suitable to achieve desirable planarization with no particle defects as SOD, however it suffers microscratches, dishing, erosion and inefficient post-CMP cleaning. CMP planarization works by removing thin film using etching slurry and pressure applied on the wafer and it does not introduce any new dielectric material. This work is to investigate and improve the particle defects and the surface planarization of interlayer dielectric (ILD) using CMP, and also to investigate the electrical properties of the metal interconnect within the ILDs planarized by the SOD and CMP