Design of Microcontroller with Completion Detection Capability by using Dual-Rail Domino Circuit

A 8-bit non-pipeline microcontroller equipped with completion detection capability is designed by using dual-rail domino circuit. The microcontroller is designed based on the instruction set of Z80 microcontroller. It is implemented with Rohm 0.35μm CMOS technology with chip size of 4.9×4.9mm2, and the measurement results reveal that it could functionally works correctly regardless of the variations due to the instruction dependency, data dependency, and the inter-chip variability. The microcontroller achieves an average speed performance of 23.3ns for evaluation time, and it needs 2.2ns for precharge time at nominal supply voltage of 3.3V. It also exhibits an automatic performance adaptation to the physical properties such as power supply voltage. Along with these, this paper presents a new footless dual-rail domino circuit that efficiently combines a footless dynamic circuit technique with a robust self-timed precharge scheme for high performance VLSI circuit design. Besides, the proposed circuit achieves a whole footless dual-rail domino circuit with the use of the proposed separator. A 20-stage NAND chains are implemented both in 0.15μm SOI CMOS technology and 90nm bulk CMOS technology for performance evaluation. Measurement results reveal that the proposed circuit achieves speed improvement over the circuit implemented with the conventional static CMOS, CPL, dynamic DCVSL, D4L, and DR-domino.報告番号: ; 学位授与年月日: 2006-03-23 ; 学位の種別: 修士 ; 学位の種類: 修士(工学) ; 学位記番号: ; 研究科・専攻: 工学系研究科電子工学専