This live demonstration showcases the Gaussian pyramid with a CMOS vision sensor. The chip features a 176 120 pixel array in standard 0.18 m CMOS technology. The sensing elements are designed as 3-Transistor Active Pixel Sensors (3T-APS) with in-pixel ADC and CDS. The Gaussian pyramid is extracted concurrently with a double-Euler switchedcapacitor network on the same substrate, giving RMSE errors below 1.2% of FSO. The chip provides a Gaussian pyramid of 3 octaves with 6 scales each with an energy cost of 26.5 nJ/px at 2.64 Mpx/s.Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2012-38921-C02, IPT- 2011-1625-430000, IPC-20111009Junta de Andalucía TIC 2338-2013, EM2013/038, EM2014/012, CN2012/151, GPC201...
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisi...
The demonstration shows the differences between two novel Dynamic and Active Pixel Vision Sensors (D...
International audienceA high speed analog VLSI image acquisition and low-level image processing syst...
Abstract—This live demonstration showcases the Gaussian pyramid with a CMOS vision sensor. The chip ...
This paper introduces a CMOS vision sensor chip in a standard 0.18 μm CMOS technology for Gaussian p...
This paper introduces a CMOS vision sensor to extract the Gaussian pyramid with an energy cost of 26...
This paper introduces an architecture of a switched-capacitor network for Gaussian pyramid generatio...
This paper reports a multi-layered smart image sensor architecture for feature extraction based on d...
http://digital.csic.es/handle/10261/84172This paper introduces a two-tier CMOS-3D architecture for g...
This paper addresses a comparison of architectures for the hardware implementation of Gaussian image...
Abstract—This paper reports a multi-layered smart image sensor architecture for feature extraction b...
International audienceA high-speed analog VLSI image acquisition and low-level image processing syst...
This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35 CMOS-OPTO pr...
International audienceA high-speed analog VLSI image acquisition and preprocessing system has been d...
International audienceA high speed Analog VLSI Image acquisition and pre-processing system is descri...
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisi...
The demonstration shows the differences between two novel Dynamic and Active Pixel Vision Sensors (D...
International audienceA high speed analog VLSI image acquisition and low-level image processing syst...
Abstract—This live demonstration showcases the Gaussian pyramid with a CMOS vision sensor. The chip ...
This paper introduces a CMOS vision sensor chip in a standard 0.18 μm CMOS technology for Gaussian p...
This paper introduces a CMOS vision sensor to extract the Gaussian pyramid with an energy cost of 26...
This paper introduces an architecture of a switched-capacitor network for Gaussian pyramid generatio...
This paper reports a multi-layered smart image sensor architecture for feature extraction based on d...
http://digital.csic.es/handle/10261/84172This paper introduces a two-tier CMOS-3D architecture for g...
This paper addresses a comparison of architectures for the hardware implementation of Gaussian image...
Abstract—This paper reports a multi-layered smart image sensor architecture for feature extraction b...
International audienceA high-speed analog VLSI image acquisition and low-level image processing syst...
This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35 CMOS-OPTO pr...
International audienceA high-speed analog VLSI image acquisition and preprocessing system has been d...
International audienceA high speed Analog VLSI Image acquisition and pre-processing system is descri...
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisi...
The demonstration shows the differences between two novel Dynamic and Active Pixel Vision Sensors (D...
International audienceA high speed analog VLSI image acquisition and low-level image processing syst...