Assessing application areas for tunnel transistor technologies
- Avedillo de Juan, María José
- Nuñez Martínez, Juan
Publication date
January 2016
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, projected tunnel transistor technologies are evaluated and compared to LP and HP versions of both conventional and FinFET CMOS in terms of their power and energy in different application areas.Ministerio de Economía y Competitividad FEDER TEC2013-40670-
Add to ORKG