A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios

This paper describes the design and implementation of a low power IF frequency synthesizer which can be used in 2-tone envelope detection radios [1]. The synthesizer is based on an All-Digital PLL (AD-PLL) architecture. By means of a system noise analysis, overall noise performance is optimized while maintaining low-power operation. A current controlled ring-oscillator is designed, optimized for low-power and low phase-noise. An integer and fractional phase quantiser (PQ) is designed, where the fractional PQ is co-integrated with the oscillator to save power. The DAC, which digitally controls the oscillator, is implemented by a `coarse' and `fine' DAC topology to reduce the resolution requirement. The `fine' DAC resolution is increased by a third-order Delta-Sigma Modulator (DSM) to alleviate matching problems while maintaining monotonicity and keeping the power consumption low. Current division of the `fine' DAC, using a highly-linear current-mirror, enables fine frequency tuning while keeping low bias currents. The chip, consisting of a current controlled oscillator, `coarse' and `fine' DAC and fractional part of the phase quantiser is implemented in a 90 nm CMOS technology. The AD-PLL operates from 10 to 20 MHz and the power consumption (excluding digital loop filter and DSM) is only 19 µW at 20 MHz operation