Parasitic inductive coupling of integrated circuits with their environment

This paper describes an original methodology for the modeling of parasitic inductive couplings. The key idea is the use of magnetic hooks which are gates for magnetic fluxes that cross conductive loops and consequently induce parasitic voltages, thus disturbing the signal integrity. The multiple connected domains of integrated circuits are modeled by a Magneto-Electric-Equivalent-Circuit (MEEC), consisting of two mutual coupled circuits, an electric and magnetic one. Magnetic hooks are the externally connected nodes of the magnetic circuit. © 2014 The Institute of Electronics, Information and Communication Engineer. Keywords: Chip; Computational Electromagnetics; IC & Semiconductor EMC; Numerical Modeling; Signal Integrit