Information-driven general functional decomposition targeted to gate libraries

Traditional circuit synthesis methods implemented in today’s automatic logic synthesis tools deal only with some very special cases of possible circuit structures and are not well adjusted to the current and future technologies and synthesis targets. Substantial improvement could only be achieved through development and implementation of a new generation of design paradigms, methods and tools, more suitable in the new situation. Modern micro-electronic technology enables building of extremely large circuits and systems, and offers a great diversity of logic building blocks, while the traditional methods are basically targeted to AND-ORNOT or MUX circuits, and require a sophisticated technology mapping for other target. However, even the most sophisticated technology mapping cannot guarantee proper final results, if the initial synthesis is performed without a good relation to the actual target. Moreover, in modern designs, the interconnections increasingly decide all important circuit features (area, speed, power dissipation), and a flexible multi-objective optimisation and trade-offs are indispensable. The information-driven approach to circuit synthesis has a potential to resolve all those issues. Within the project the main issues of library modelling for information-driven synthesis, multi-valued sub-function encoding etc. were researched, and a prototype synthesis method and corresponding EDA-tool were developed, that considerably differs from all other known methods and tools. The experimental results from the tool that implements the new method demonstrate that the method and tool targeted to the gate-based circuit deliver much better circuits than the other methods and demonstrate that the information-driven general decomposition produces very fast and compact gate-based circuits