Current loop buffer organizations for very large instruction word processors are essentially centralized. As a consequence, they are energy inefficient and their scalability is limited. To alleviate this problem, we propose a clustered loop buffer organization, where the loop buffers are partitioned and functional units are logically grouped to form clusters, along with two schemes for buffer control, which regulate the activity in each cluster. Furthermore, we propose a design-time scheme to generate clusters by analyzing an application profile and grouping closely related functional units. The simulation results indicate that the energy consumed in the clustered loop buffers is, on average, 63 percent lower than the energy consumed in an ...
Technical Report 01-04, INSA Lyon, Lab L3I. 11 pages.International audiencePortable or embedded syst...
Multimedia applications, executed by embedded multiprocessor systems, can in some cases be represent...
In this paper, we investigate the suitability of clustered architectures for designing scalable mult...
Current loop buffer organizations for very large instruction word processors are essentially central...
Current loop buffer organizations for very large instruction word processors are essentially central...
Abstract—Current loop buffer organizations for very large instruction word processors are essentiall...
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the ins...
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the ins...
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the ins...
\u3cp\u3eEnergy consumption in embedded systems is strongly dominated by instruction memory organiza...
The traditional VLIW (very long instruction word) architecture with a single register file does not ...
Wire delays are a major concern for current and forthcoming processors. One approach to attack this ...
Portable or embedded systems as well as submicronic tech-nologies have made the power consumption cr...
Abstract We observe the misbehavior of traditional LRUlike buffer management schemes in video-on-dem...
Technical Report 01-04, INSA Lyon, Lab L3I. 11 pages.International audiencePortable or embedded syst...
Multimedia applications, executed by embedded multiprocessor systems, can in some cases be represent...
In this paper, we investigate the suitability of clustered architectures for designing scalable mult...
Current loop buffer organizations for very large instruction word processors are essentially central...
Current loop buffer organizations for very large instruction word processors are essentially central...
Abstract—Current loop buffer organizations for very large instruction word processors are essentiall...
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the ins...
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the ins...
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the ins...
\u3cp\u3eEnergy consumption in embedded systems is strongly dominated by instruction memory organiza...
The traditional VLIW (very long instruction word) architecture with a single register file does not ...
Wire delays are a major concern for current and forthcoming processors. One approach to attack this ...
Portable or embedded systems as well as submicronic tech-nologies have made the power consumption cr...
Abstract We observe the misbehavior of traditional LRUlike buffer management schemes in video-on-dem...
Technical Report 01-04, INSA Lyon, Lab L3I. 11 pages.International audiencePortable or embedded syst...
Multimedia applications, executed by embedded multiprocessor systems, can in some cases be represent...
In this paper, we investigate the suitability of clustered architectures for designing scalable mult...