The application of a combined test-error-correcting procedure is studied to improve the mean time to failure (MTTF) for degrading memory systems with defects. The degradation is characterized by the probability p that within a unit of time a memory cell changes from the operational state to the permanent defect state. Bounds are given on the MTTF and it is shown that, for memories with N words of k information bits, coding gives an improvement in MTTF proportional to (k/n) N(dmin-2)/(dmin -1), where dmin and (k/n) are the minimum distance and the efficiency of the code used, respectively. Thus the time gain for a simple minimum-distance-3 is proportional to N-1. A memory word test is combined with a simple defect-matching code. This yields ...
International audienceWe illustrate that memory repair for high defect densities allows improving yi...
textOngoing technology improvements and feature size reduction have led to an increase in manufactur...
[[abstract]]Abstract: In this paper, methods for memory test time reduction are proposed. The first ...
The application of a combined test-error-correcting procedure is studied to improve the mean time to...
Abstract—The reliability of memory systems that are exposed to soft errors has been studied in the p...
This article presents an analysis of the reliability of memories protected with Built-in Current Sen...
As DRAM cells continue to shrink, they become more susceptible to retention failures. DRAM cells tha...
Part I. Correction of Cell Defects in Integrated Memories: This paper introduces two schemes to corr...
International audienceError-correcting codes (ECC) offer an efficient way to improve the reliability...
The paper is concerned with developing quantitative results on the lifetime of coded random-access s...
As memory technology scales, the demand for higher performance and reliable operation is increasing ...
Nearly every synchronous digital circuit today is de-signed with timing margins. These timing margin...
This paper presents a method to protect memories against multiple bit upsets and to improve manufact...
ISBN 978-1-4673-5542-1International audienceIn modern SoCs embedded memories should be repaired to a...
International audienceTwo error correction schemes are proposed for word-oriented binary memories th...
International audienceWe illustrate that memory repair for high defect densities allows improving yi...
textOngoing technology improvements and feature size reduction have led to an increase in manufactur...
[[abstract]]Abstract: In this paper, methods for memory test time reduction are proposed. The first ...
The application of a combined test-error-correcting procedure is studied to improve the mean time to...
Abstract—The reliability of memory systems that are exposed to soft errors has been studied in the p...
This article presents an analysis of the reliability of memories protected with Built-in Current Sen...
As DRAM cells continue to shrink, they become more susceptible to retention failures. DRAM cells tha...
Part I. Correction of Cell Defects in Integrated Memories: This paper introduces two schemes to corr...
International audienceError-correcting codes (ECC) offer an efficient way to improve the reliability...
The paper is concerned with developing quantitative results on the lifetime of coded random-access s...
As memory technology scales, the demand for higher performance and reliable operation is increasing ...
Nearly every synchronous digital circuit today is de-signed with timing margins. These timing margin...
This paper presents a method to protect memories against multiple bit upsets and to improve manufact...
ISBN 978-1-4673-5542-1International audienceIn modern SoCs embedded memories should be repaired to a...
International audienceTwo error correction schemes are proposed for word-oriented binary memories th...
International audienceWe illustrate that memory repair for high defect densities allows improving yi...
textOngoing technology improvements and feature size reduction have led to an increase in manufactur...
[[abstract]]Abstract: In this paper, methods for memory test time reduction are proposed. The first ...