A flexible bottom-up approach for layout generation

The subject of this paper is an algorithm generating topological layouts for VLSI-circuits that are specified by means of programs. A topological layout, which is both a metric-free and a material-free layout, is an intermediate step in the process of converting a program into a silicon chip. The algorithm described in this paper is based upon a bottom-up approach, while lazy evaluation, constituted by the postponement of the construction of some connections, guarantees a flexible connecting to different environments