Design Strategy for a Pipelined ADC Employing Digital Post-correction

This paper describes how the usage of digital post-correction techniques in pipelined analog-to-digital converters (ADC's) can be exploited optimally during the design-phase of the converter. It is known that post-correction algorithms reduce the influence of several cir- cuit impairments on the final accuracy of the converter [1], [2]. However, until now, no models relating these circuit impairments to the final accuracy of the ADC, taking the usage of a post-correction algorithm into account, have been known to exist. To take maximum advantage of a certain correction algorithm, this model is a must. Therefore, this paper introduces a behavioral model of a pipelined ADC, including several important error mechanisms, representing possible circuit impairments like offset, gain error, harmonic distortion, etc. With this model, including the post-correction algorithm, simple design con- straints for each part of the circuit can be derived such that a certain target accuracy of the ADC is achieved. In the analog design-phase these high-level constraints can be translated to implementation-dependent low-level design requirements. If these low-level requirements are fulfilled, the model guarantees that the converter will achieve its target accuracy. A design-example for a 12-bit pipelined ADC is worked out. Simulation results will be shown, validating the correctness of the presented design-method. The proposed design-strategy can be applied to all pipelined ADC's with post-correction like in [1], [2], taking maximum advantage of the benefits of the correction algorithm during the analog design-phase