Technology mapping for area and speed

Recently, it has been shown that speed optimization for general acyclic network is efficiently solvable, and elegant ways of capturing several representations with base functions in a single network were introduced. This paper shows how to take advantage of these discoveries without failing miserably with other quality characteristics than speed, nor consuming excessive amounts in run time and memory. The proposed technology mapping procedure incorporates state-of-the-art procedures, in which a graph covering is applied to a special graph structure succinctly encoding many different representations. At each node an area-delay trade-off curve is constructed using matches found at the node for different decompositions. This enables area control by preventing non-critical paths from being too fast and therefore too large. To obtain reliable area assessment crossing numbers are introduced to handle area allotment under multiple fanout. Partial matching, on top of input limitations, is used to avoid explosions in computation time and memory usage. Experiments so far show that the combined use of procedures at least meets, but usually outperforms the result of using one of the separate procedures