A Power-Gating Scheme for MOS Current Mode Logic Circuits

MOS Current-Mode Logic (MCML) is widely used for high-speed circuits. However, the MCML circuits have large static power consumptions due to their constant operation currents. This paper presents a power-gating scheme for MCML circuits to reduce their static power dissipations in sleep mode. The PMOS transistors for linear load resistors of MCML circuits are used for power-gating switches. A power-gating control circuit consisting of NMOS and PMOS transistors is added for switching power-gating switches under the control of the sleep signal. The structure and operation of the proposed power-gating scheme are presented. In order to verify the correctness of the proposed power-gating scheme, several basic cells and a full-adder based on MCML circuits are realized. All the circuits are simulated with HSPICE at SMIC 130nm technology. The simulation results show that the power dissipations of the MCML circuits can be greatly reduced by shutting down their idle logic blocks. DOI: http://dx.doi.org/10.11591/telkomnika.v11i10.287