Wireless Extension Mechanism and Logic Design for FPGA-based Ethernet Powerlink Node

Real-time networks, such as industrial network, field bus and so on, have been becoming one vital component to develop large-scale and cooperative embedded systems. As one important branch, the wireless mode of realtime networks also raises more and more attentions in recent years since its conveniences to construct a flexible control system. Ethernet Powerlink is such a typical real-time industrial network protocol, and provides a master-slave, time-slot mechanism that can well avoid radio collisions. With the designed FPGA-based hardware node, in this paper, a new method to extend wireless capability of Powerlink is explored and described. Concretely, Powerlink architecture and especially its original mechanisms are analyzed at first. For effectively connecting OpenMAC module of Powerlink and RF module, an interface logic at MAC layer is introduced and is typically designed in a multiplexing mode with a dual-FIFO logic according to the limited resource on FPGA, some key designs and mechanisms of which are detailed later. Finally, all designed mechanisms and logics are implemented as an extension part of IP core of Powerlink in VHDL language, and the communication functions and performance of such extended protocol areverified