Comparative analysis of analog LDO design

The presented research analyses different topologies of low dropout (LDO) regulator, mostly focusing on different frequency compensation schemes and power supply rejection analysis. This thesis discusses different analog LDO topologies and analyzes how they achieve stability using small signal analysis and related equations. The power supply rejection (PSR) of a different error amplifier and pass device has been analyzed and concluded that a Type-B amplifier with n-channel metal oxide semiconductor field effect transistor (MOSFET) output stage or a Type-A amplifier with p channel MOSFET (PMOS) output stage yields the best PSR. Digital LDO regulator topologies have also been discussed. The digital LDO regulator is intriguing due to its low power and synthesizability, but it suffers from coarse voltage regulation and poor PSR compared to the analog LDO regulator