Optimization methods for synthesizable IP instantiation in HLS tool

High level synthesis tools generate hardware RTL code, such as Verilog, from a high level language, such as C. This is an important step in accelerating the hardware design process by automating the software to hardware design flow, including efficiency optimizations. When calculating area and latency estimation values, FPGA and ASIC design flows follow similar processes, many of these steps are automated by vendor design tools. ASIC circuits pose several further challenges because it follows a different and more work intensive design flow for simulations to acquire similar data. Using Synopsys’s DesignWare IP library, different methods of automated IP instantiation, characterization and clock optimization are used to explore calculating these costs and verifying generated netlists at the logic synthesis level efficiently.U of I OnlyUndergraduate senior thesis not recommended for open acces