Crosstalk Noise and Timing Analysis of Digital VLSI Circuits With Coupled Interconnects

109 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000.At the logic hierarchical level, we have developed a logic-level timing analyzer that will perform static timing simulation as well m coupling noise estimation using the information produced during the circuit hierarchy stage. The results of this analyzer consist of (a) critical path delay for the entire circuit, (b) transition windows, and (c) crosstalk noises for all victim gates. The maximum amplitude and effective width of crosstalk can be obtained at the fan-out of each victim gate and used to check the failure criteria of the gate that receives this noise pulse as an input.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD