Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors

114 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999.More specifically, we propose a technique that uses an additional mini cache located between the instruction cache (I-Cache) and the CPU core; the mini cache buffers instructions that are nested within loops and are continuously fetched from the I-Cache. This mechanism can create very substantial energy savings, since the I-Cache unit is one of the main power consumers in most of today's high-performance microprocessors. Results are reported for the SPEC95 benchmarks in the R-4400 processor which implements the MIPS2 instruction set architecture.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD