New Techniques to Verify Timing Correctness of Integrated Circuits

111 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.A preliminary study of the relationship between false paths and delay fault testing is also presented. We first show an example where a circuit that does not have any delay variations behaves incorrectly during normal operation due to the common assumptions on false paths used in determining the clock cycle time. We then show an example of a faulty circuit that passes testing because certain false paths contribute to the invalidation of delay tests generated under a single-fault assumption. Finally, we show an example where a good circuit that functions correctly under normal operation is declared as faulty when certain false paths are activated during scan-based testing. For each case, we suggest possible remedies that can sometimes result in more conservative estimates on clock cycle times.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD