Architecture and CAD for Nanoscale and Three-Dimensional FPGA

119 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2010.To maximize the potential performance gain of 3D integrated circuit architectures, an SSTA engine was developed to deal with both uncorrelated and correlated variations in 3D FPGAs. The effects of intra-die and inter-die variation are considered. Using the 3D physical design tool TPR as a base, a new 3D routing algorithm is developed, which improves the average performance of two-layer designs by over 22% and three-layer designs by over 27%.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD