Add to ORKG172 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.For configurable SRAM, data storage savings in the range of 29% static power and 6% dynamic power are achieved without sacrificing code performance. When slight performance degradation can be tolerated, the compiler uses profile feedback to realize an average of 51.7% static and 9.4% dynamic power reduction.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD
Power density is currently the primary design constraint across most computing segments and the main...
Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon ...
Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon ...
172 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.For configurable SRAM, data s...
To accomodate standards changes and algorithmic im-provements, functional reconfigurability is incre...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
Digital computation has penetrated diversity of applications such as audio visual communication, bio...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
The thesis presents a data-dependent write assist (DDWS) dynamic SRAM cell to reduce the power consu...
With ever raising demands of battery operated portable device in market is encouraging the VLSI make...
The increasing sub-threshold leakage current levels with newer technology nodes has been identi-fied...
Recently, power-performance (performance per uniform power consumption) has become a more important ...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
Abstract. Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Part...
textOne of the major limiters to computer systems and systems on chip (SOC) designs is accessing the...
Power density is currently the primary design constraint across most computing segments and the main...
Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon ...
Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon ...
172 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2004.For configurable SRAM, data s...
To accomodate standards changes and algorithmic im-provements, functional reconfigurability is incre...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
Digital computation has penetrated diversity of applications such as audio visual communication, bio...
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Comput...
The thesis presents a data-dependent write assist (DDWS) dynamic SRAM cell to reduce the power consu...
With ever raising demands of battery operated portable device in market is encouraging the VLSI make...
The increasing sub-threshold leakage current levels with newer technology nodes has been identi-fied...
Recently, power-performance (performance per uniform power consumption) has become a more important ...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
Abstract. Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Part...
textOne of the major limiters to computer systems and systems on chip (SOC) designs is accessing the...
Power density is currently the primary design constraint across most computing segments and the main...
Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon ...
Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon ...