On the Analysis, Design, and Modeling of Electrostatic Discharge Protection Devices for Analog and Radio -Frequency Integrated Circuits

97 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2002.We present a simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to modeling accurately the high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD