Design and Simulation of Serializer and Deserializer for High-Speed SerDes Link

In modern network processors, a high-speed serial input/output (I/O) component is essential in data transmission. A serializer-deserializer (SerDes) is implemented to achieve the goal of high-speed serial data transmission with signal integrity. The SerDes design provides advantages of faster transmission speed, small interferences between links, and low manufacturing cost. In such a design, parallel data inputs are mapped into one data stream by the serializer. The mapped serial data is then transmitted via channel. At the receiver end, the data will be deserialized to recover the original parallel data inputs by deserializer. Thus, serializer and deserializer with small delay and low power consumption are desired in SerDes design. This thesis covers several methodologies of serializer and deserializer design, the design flow and simulation of serializer and deserializer at the transistor level in 180nm CMOS technology with Cadence Virtuoso and resulting in simulation waveforms. The resulted simulations demonstrated the design could successfully operated under 4GHz frequency.U of I OnlyUndergraduate senior thesis not recommended for open acces