Pipelined Implementation of a Fixed-Point Square Root Core Using Non-Restoring and Restoring Algorithm

Arithmetic Square Root is one of the most complex but nevertheless widely used operations in modern computing. A primary reason for the complexity is the irrational nature of the square root for non-perfect numbers and the iterative behavior required for square root computation. A typical RISC implementation of Square Root Computation can take anywhere from 200 - 300 cycles. If significant usage is encountered, this could result in an impact in run-time cost which would justify a direct hardware implementation that achieves the same result in as little as 20 clock cycles. Additionally, the implementation is pipelined to achieve even greater throughput compared to an instruction based implementation. The paper thus presents an efficient, pipelined implementation of a square root calculation core which implements a non-restoring algorithm of determining the square-root. The iteration count of the algorithm depends on the maximum size of the input and the desired resolution. A specific case of a 16-bit integer square root calculator with output resolution 0.001 is considered which requires a total of 18 iterations of the algorithm. In the implementation, each iteration is pipelined as a stage thereby resulting in an 18-stage pipelined square root computation core. The proposed algorithm utilizes standard arithmetic operations like addition, subtraction, shift and basic control statements to determine the output of each stage. The core is verified using SystemVerilog test-bench. The test-bench generates unconstrained random inputs stimulus and determines the expected value from the core device under test (DUT) by evaluating a Simulink generated model for the same stimulus. Functional coverage, implemented in the test-bench, determines reliability of the system and consequently the duration of the test execution