Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
- Nuñez Martínez, Juan
- Ginés Arteaga, Antonio José
- Peralías Macías, Eduardo
- Rueda Rueda, Adoración
DOIAbstract
This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for high-performance ADCs. The key ideas of the design methodology are: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock...
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