Low power approximate multipliers for energy efficient data processing

Computation accuracy can be adequately tuned on the specific application requirements in order to reduce power consumption. To give some examples, image processing and audio/speech recognition e.g., multimedia applications may provide more accurate outputs than human capabilities can appreciate. In this case, producing inexact numerical outputs can be acceptable and approximate computing circuits could be employed to reduce power consumption by decreasing the hardware complexity. This paper proposes approximate multipliers based on exact and inexact adder circuits and their FPGA implementation: the proposed multipliers can be applied for both signed and unsigned operations. Two scenarios were considered and analyzed in this paper. First, the performance of the proposed multiplier based on inexact adder is evaluated by comparing the power consumption, the accuracy of computation, and the time delay with those of an approximate multiplier based on exact adder. Second, the design parameters of the proposed multipliers are compared with those of the Baugh-Wooley multiplier. On the other hand, we analyzed and compared the performance of the unsigned approximate multipliers with respect to the signed approximate ones. Results prove that the proposed approximate multipliers achieve a reduction in power consumption of 56.3% with respect to the Baugh-Wooley multiplier at cost of less than 5% of accuracy loss