Scheduler-based Multi-Bank Main Memory Configuration for Energy Reduction

International audienceModern DRAM technologies offer power management features for energy consumption optimization. It consists of multi-banking the addressing space instead of monolithic memory. The main advantage in this approach is the capability of setting banks in low power modes when they are not accessed, such that only the accessed bank is maintained in active mode. In this paper we investigate how this power management capability can be handled for real-time and multitasking applications. We aim to find, based on the application scheduler, both an efficient allocation of application's tasks to memory banks, and the corresponding memory configuration that lessen the energy consumption: number of banks and the size of each bank. Results show the effectiveness of this approach and the large energy savings