Analysis of a Parasitic‐Diode‐Triggered Electrostatic Discharge Protection Circuit for 12 V Applications

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic‐diode‐triggered silicon controlled rectifier. The breakdown voltage and trigger voltage (Vt) of the proposed ESD protection circuit are improved by varying the length between the n‐well and the p‐well, and by adding n+/p+ floating regions. Moreover, the holding voltage (Vh) is improved by using segmented technology. The proposed circuit was fabricated using a 0.18‐μm bipolar‐CMOS‐DMOS process with a width of 100 μm. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the Vt of the proposed circuit increased from 14 V to 27.8 V, and Vh increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human‐body‐model surges at 7.4 kV and machine‐model surges at 450 V