Field programmable gate array softcore processors optimised for digital signal processing applications

The benefits of adding explicit DSP operation support to an FPGA-based softcore processor are examined. An experimental DSP processor has been designed, implemented, simulated, and verified on a Xilinx Virtex-5 XC5VSX50T FPGA chip. An initial very simple architecture is upgraded with different supporting hardware to enhance the processor's performance in execution of DSP applications. These hardware enhancement techniques include a specialist execution unit, modification to the memory architecture, adding an extra address control unit, upgrading with more active addressing modes, and extending the instruction set with zero-overhead looping support. These enhancements reduce the number of instructions used in the inner loop of convolution-based DSP algorithms to a single instruction. By using these proposed enhancement techniques, the overall performance was improved by an average of 9 times (800% improvement) in FIR Filter and Matrix Multiplication benchmark DSP applications. The overall area increased by about 1.41 times (41% extra cost). Using in-built DSP blocks in the FPGA instead of logic blocks to implement the arithmetic unit of the processor reduced the power consumption by 14% from 840 mW to 725 mW